With advancements in design and fabrication processes of IC devices, semiconductor manufacturers are able to increase the component density in integrated circuits and deliver smaller scaled IC devices that provide benefits such as improved performance, reduced power consumption, lower cost, etc. for a target product. Fabrication of the components in such devices may require smaller circuit elements, for example, interconnects, conductive lines, contacts, resistors, and the like. In some instances, a reduction in the size of a circuit element may be beneficial in some aspects while limiting in others. For example, in a FinFET device, a width of a Si fin may be based on a required/desired short-channel performance (e.g. better with a narrow width) while the same width may negatively impact formation and characteristics of S/D regions in the Si fin leading to undesired performance issues.
FIG. 1A illustrates a top view of example Si fins 101, in a substrate 103, with a uniform width W across a gate/channel region 105, and S/D regions 107 and 109. As mentioned, the width W may be optimized to improve short-channel effects (SCE) in the channel region, wherein a narrower width can provide for a better short-channel performance. However, a narrower fin width may hinder formation of an optimum S/D epi width; thus, impacting drive current of the device.
FIG. 1B illustrates a cross-sectional view of the source 107 (or drain 109) regions along a cross-sectional reference line 1B-1B′. In FinFET devices, one or more epitaxy processes may be utilized to increase the size of fin sections in the S/D regions 107/109 where semiconductor material 111 (e.g., Si, silicon-germanium) may be grown/deposited (epi growth) on and around the fins in the S/D regions. The epi growths 111 on the fins may help to reduce electrical resistance in the S/D regions, provide larger areas for electrical contacts to the S/D regions, and provide additional physical support/strength for the fins. However, a volume of an epi growth 111 may be limited by the width of a fin 101.
Therefore, a need exists for methodology enabling formation of a Si fin with different widths and the resulting devices.